1. Technical Field
The embodiments described herein relate to a stack bank type semiconductor memory apparatus, and more particularly, to a semiconductor memory including a plurality of banks having a plurality of sub-banks.
2. Related Art
A conventional semiconductor memory apparatus includes a plurality of memory cells and a circuit for controlling the memory cells. At present, a bank concept has been introduced to control a plurality of memory cells by classifying the memory cells into groups. A bank represents an area that includes a plurality of memory cells. The memory cells are grouped into banks and controlled to improve the signal transmission characteristics of the semiconductor memory apparatus.
Recently, as the number of memory cells included in semiconductor memory apparatus has increased significantly, a multi-bank scheme has been proposed to control banks by dividing the banks into sub-banks.
FIG. 1 is a plan view illustrating a conventional semiconductor memory apparatus employing such a multi-bank scheme. Referring to FIG. 1, a semiconductor chip 10 may be divided into four banks 12a to 12d. The banks 12a to 12d are spaced apart from each other and a peripheral area 14 is interposed therebetween. For example, each of the banks 12a to 12d may be divided into an up bank UP and a down bank DOWN about a half line HL. Each up bank may be divided into four sub-banks 15 and each down bank may also be divided into the four sub-banks 15.
Each sub-bank 15 includes a plurality of word lines, a plurality of bit lines crossing the word lines, and a plurality of memory cells defined by the word and bit lines. The word and bit lines may extend in the y and x directions of FIG. 1.
At the present time, the semiconductor memory apparatus performs hierarchical data input/output. To this end, the semiconductor memory apparatus employs a plurality of data bus lines. A conventional semiconductor memory apparatus hierarchically transfers data, which is loaded on a bit line, to a sub-input/output (SIO, not shown) line, a local input/output (LIO, not shown) line, and a global input/output (GIO, not shown) line. The global input/output line is arranged between the sub-banks 15 perpendicular to the extension direction of the bit line.
Further, Y-control blocks 20 are arranged between the sub-banks 15 adjacent to the global input/output line to control a ‘Yi’ signal of a corresponding sub-bank 15, respectively. Furthermore, an X-hole 25, which includes circuits used for driving the word line, is arranged between the sub-banks 15 perpendicular to the Y-control block 20.
FIG. 2 is an enlarged plan view illustrating one bank in FIG. 1. AS can be seen, one fuse set 23 is installed in each sub-bank 15 to repair a memory cell defect occurring between the Y-control block 20 and the global input/output line. Further, circuits (not shown) are arranged in the peripheral area 14 to control the banks 12.
Each bank 12a of the semiconductor chip 10 receives commands and signals from the control circuits arranged in the peripheral area 14. However, the number of memory cells integrated in the banks 12 is increased due to the increase in the integration degree of conventional semiconductor memory apparatus. The increased number of memory cells increases the area of the sub-banks 15 and the area of the banks 12 including the sub-banks 15. In addition, the area of the blocks 20 and 25, which control the banks 12, must also increase.
Therefore, the alignment margin between the banks 12 is insufficient, and a sufficient gap between the sub-banks 15 may not be sufficiently ensured. The reduction in the gap between the sub-banks 15 may cause a reduction in the line width and spacing related to the global input/output line. The reduction in the spacing related to the global input/output line causes crosstalk, and the reduction in the line width of the global input/output line causes a signal delay.